AN525 Datasheet, PDF (1/10 Pages) Silicon Laboratories – OPTIMIZED CLASS 1 PD DESIGNS USING

AN525
OPTIMIZED CLASS 1 PD DESIGNS USING THE Si3402
1. Introduction
The Si3402 is designed to support up to 20 W of input power with over 15 W of power delivered to the load. For this
reason, the standard reference designs have been optimized for high-power situations.
The IEEE standard for PoE (802.3 clause 33) specifies the PD classes as listed in Table 1.
Table 1. PD Classes
PD Classification
Class 0 or Class 3
Class 1
Input Power Maximum
13 W
3.84 W
Output Power Allowing for 80%
Conversion Efficiency
10.4 W
3.07 W
Class 2
6.49 W
5.19 W
Class 4
25.5 W
20.4 W
Even the 3 W of output power that can realistically be derived from a Class 1 interface is adequate for many
applications. This application note shows how the standard reference design is modified and simplified to support
lower power situations.
2. Optimized Reference Designs
Figure 1 shows the completed schematic of the Class 1 reference design for the isolated case, and Figure 2 shows
the reference design for the non-isolated case. Tables 2 and 3 are the bills of materials corresponding to Figures 1
and 2.
Rev. 0.2 7/11
Copyright © 2011 by Silicon Laboratories
AN525