AN491 Datasheet, PDF (1/8 Pages) Silicon Laboratories – POWER SUPPLY REJECTION FOR LOW-JITTER CLOCKS

AN491
POWER SUPPLY REJECTION FOR LOW-JITTER CLOCKS
1. Introduction
Hardware designers are routinely challenged to increase functional density while shrinking the overall PCB
footprint of each new design. One significant challenge is minimizing clock jitter through careful board design while
meeting the design's functional and space requirements. Since jitter is a measure of signal fidelity, it requires an
understanding of diverse analog concepts, such as transmission line theory, interference, bandwidth, and noise, in
order to manage their impact on performance. Among these, density impacts sensitivity to external noise and
interference the most. Since noise and interference are everywhere and since multiple components share a
common power supply, the power supply is a direct path for noise and interference to impact the jitter performance
of each device. Therefore, achieving the lowest clocking jitter requires careful management of the power supply.
Sensitivity to power supply is commonly referred to as power supply ripple rejection or power supply rejection ratio
(PSRR). For jitter, ripple rejection is more appropriate.
2. Impact
The effect of power supply ripple on jitter is quite straightforward. Power supply influences the propagation delay by
affecting both the switching voltage threshold of logic gates as well as the output resistance. As the switching
voltage threshold is modulated, the time at which the output transitions is modulated because the input signal has
a finite slope as shown in Figure 1.
V
Modulated Switching Threshold
Input
Propagation Delay
t
Jitter
Output
t
Figure 1. Changing Thresholds Due to Power Supply Noise
Varying output resistance affects the propagation delay of the CMOS gate through the parasitic RC filter. When
combined, these two effects change the propagation delay through the CMOS gate. The effect is amplified as more
gates are placed in series.
The degree of the impact is highly dependent on the "speed" of the transistors involved. By having a faster slope at
the CMOS gate input, the impact from a changing threshold can be minimized. In addition, faster circuits require
that capacitance be minimized in order to achieve small propagation delays; so, the delay variation due to supply
variations can be minimized by making the routing capacitance as small as possible. However, there are trade-offs;
the downside to faster circuits is power consumption. To make a faster edge, more current is required to charge the
capacitors given a constant voltage.
Rev. 0.2 4/13
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AN491