AN350 Datasheet, PDF (1/8 Pages) Silicon Laboratories – Si4708/09 ANTENNA, SCHEMATIC, LAYOUT, AND DESIGN GUIDELINES

AN350
Si4708/09 ANTENNA, SCHEMATIC, LAYOUT, AND DESIGN
GUIDELINES
1. Introduction
This document provides general Si4708/09 design guidelines and an FM antenna selection that includes
schematic, BOM, and layout and design checklist. All users should follow the Si4708/09 design guidelines
presented in Section 2 and headphone antenna design guidelines in Section 3. To get an in-depth knowledge
about the headphone antenna, the antenna theory and interface model is presented in the Appendix.
2. Si4708/09 2.5 x 2.5 mm QFN Schematic and Layout
This section shows the minimal schematic and layout options required for optimal Si4708/09 performance.
Population options are provided to support the layout for all 2.5 x 2.5 mm QFN devices, mitigate system noise, and
filter VCO energy.
2.1. Si4708/09 2.5 x 2.5 mm Design
C1 (22 nF) is a required bypass capacitor for VD supply pin 10. Place C1 as close as possible to the VD pin 10 and
GND pin 11. Place a VIA connecting C1 VD supply to the power rail such that the cap is closer to the Si4708/09
than the VIA. Route C1 GND directly and only to GND pin 11 with a wide, low inductance trace. These
recommendations are made to reduce the size of the current loop created by the bypass cap and routing, minimize
bypass cap impedance, and return all currents to the GND pad.
C2 (22 nF) is an optional bypass capacitor for VA supply pin 14 and may be placed to mitigate supply noise. Place
C2 as close as possible to the VA pin 14. Place a VIA connecting C2 VA supply to the power rail such that the cap
is closer to the Si4708/09 than the VIA. These recommendations are made to reduce the size of the current loop
created by the bypass cap and routing, minimize bypass cap impedance, and return all currents to the GND pad.
C3 (100 nF) is an optional bypass capacitor for the VIO supply pin 8 and may be placed to mitigate supply noise.
Place C3 as close as possible to the VIO pin 8 and the GND pin 11. Place a VIA connecting C3 VIO supply to the
power rail such that the cap is closer to the Si4708/09 than the VIA. Route C3 GND directly and only to GND pin 11
with a wide, low inductance trace. These recommendations are made to reduce the size of the current loop created
by the bypass cap and routing, minimize bypass cap impedance, and return all currents to the GND pad.
C4 (2–5 pF) is an optional filter capacitor for FMI pin 2 and may be placed to shunt VCO energy to GND and
prevent it from radiating from an antenna connected to the FMI pin. This filter is only required if regulatory testing
requires measuring emissions at the VCO frequency of 3 to 4 GHz and the antenna implementation is an efficient
radiator at these frequencies. Place C4 as close as possible to FMI pin 2 and RFGND pin 3. Place a VIA
connecting C4 FMI to another layer as needed such that the cap is closer to the Si4708/09 than the VIA.
C8 and C9 (0.39 µF) are ac coupling caps for receiver analog audio output from ROUT pin 12 and LOUT pin 13.
The input resistance of an amplifier, such as a headphone amplifier, and the capacitor will set the high pass pole
given by Equation 1. Placement location is not critical.
R1 (1 k or C5 (2-5 pF) are required for filtering when using GPO interrupts (polling not an issue). Place R1 on the
opposite side of the PCB as the tuner (as close to pin 15 as possible) and route the GPO trace to the system
controller on this layer. Alternatively, capacitor C5 (2-5 pF) may be placed as a filter capacitor also on the opposite
side of the tuner and connected directly to ground.
R2-R6 (25 –2 k) are optional series termination resistors and are used to mitigate system noise. The
recommended value of the resistors is 2 k for optimal edge rate and noise suppression. Confirm that timing
requirements are met with the selected series termination resistor value. Place the series termination resistors R2-
R6 as close to the host controller as possible.
Rev. 0.2 10/09
Copyright © 2009 by Silicon Laboratories
AN350