AN311 Datasheet, PDF (1/4 Pages) Silicon Laboratories – CP2120 PORTING GUIDE

AN311
CP2120 PORTING GUIDE
Relevant Devices
This application note applies to the CP2120.
1. Introduction
The CP2120 SPI to SMBus bridge device can be used as a replacement for the Philips SC18IS60x device by
making only a few minor hardware and firmware design modifications. All firmware and hardware differences
between the SC18IS60x and CP2120 are outlined in Table 1.
Table 1. Improvement and Modification Summary
SCI18IS60x
Up to 6 general purpose I/O pins
96-byte buffers
No transition byte needed
Up to 3 MHz SPI frequency
4.4 mm package size
CP2120
8 general purpose I/O pins
256-byte buffers
Ability to write a data buffer to up to 255
slave address
Edge Triggered Interrupt Source
Ability to read received byte buffer size
SCL Low for SMBus compatibility
Free Bus Detect for SMBus compatibility
Transition byte between SPI command
write and read phases
Up to 1 MHz SPI frequency
SMBus clock configuration
4 mm package size
Section
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.6
2.1.1
2.1.2
2.1.3
3
2. Firmware
The CP2120 responds to all SC18IS60x commands, including all Internal Register reads, writes, and all Internal
Register reads and writes and all SMBus related commands. The CP2120 offers additional Internal Registers and
commands that enhance performance of designs currently using the SC18IS60x device. However, designers must
make certain modifications, which are discussed in the following sections, to their existing SPI Master interface in
order to communicate with the CP2120.
2.1. Added Features
The CP2120 incorporates a number of features not found in the SC18IS60x. SPI Master firmware can take
advantage of these added features to create a more efficient and reliable system.
Rev. 0.1 9/06
Copyright © 2006 by Silicon Laboratories
AN311