AN31 Datasheet, PDF (1/8 Pages) Silicon Laboratories – INDUCTOR DESIGN FOR THE Si41XX SYNTHESIZER FAMILY

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INDUCTOR DESIGN FOR THE Si41XX SYNTHESIZER FAMILY
1. Introduction
Silicon Laboratories’ family of frequency synthesizers
integrates VCOs, loop filters, reference and VCO
dividers, and phase detectors in standard CMOS
technology. Depending on the synthesizer being used,
the frequency of operation may require an external
inductance to establish the desired center frequency of
operation. This may be implemented with either a
printed circuit board (PCB) trace or a discrete “chip”
inductor. This application note provides guidelines for
designing these external inductors to ensure maximum
manufacturing margin for frequency tuning.
3.1. Using a Discrete “Chip” Inductor
If the required value for L_EXT is greater than 3 nH, it is
recommended that a discrete “chip” inductor be used.
This inductor should be placed as close as possible to
the device pins as shown in Figure 1.
printed trace
discrete
inductor
2. Determining L_EXT
The center frequency for many of Silicon Laboratories’
frequency synthesizers is established using an external
inductor. The value for this inductor is determined by
Equations 1 and 2:
f_CEN = -------------------------------¹--------------------------------
2π _{CNOM(LPKG + LEXT)}
from which
(Equation 1)
L_EXT
=
---------------------¹---------------------
( 2 π f _{C E N} ) ²C_{N O M}
–
L_PKG
(Equation 2)
where f_CEN = desired center frequency of synthesizer
C_NOM = nominal tank capacitance from
synthesizer data sheet
L_PKG = package inductance from synthesizer
data sheet
L_EXT = external inductance required
3. Implementing L_EXT
Once the required value of external inductance is
determined given the desired center frequency, a choice
must be made regarding the implementation of the
inductor. The two possible implementations are a
discrete “chip” inductor or a printed circuit board trace.
J
inductor device pad
synthesizer device pad
Figure 1. Placement of Discrete
“Chip” Inductor
While close placement will minimize the inductance of
the traces connecting the discrete inductor to the
synthesizer, these traces, nonetheless, contribute to the
total overall inductance.
The total external inductance includes contributions
from both the discrete inductor and the connecting
traces as indicated in Equation 3:
L_EXT = L_NOM + X(J + 0.3)
(Equation 3)
where
L_EXT = external inductance
L_NOM = nominal value of discrete “chip”
inductor
X = constant of proportionality for MLP
(X_MLP) or TSSOP (X_TSSOP) (nH/mm)
J = dimension shown in Figure 1 (mm)
Note that the term “J + 0.3” is the effective D dimension
used in the next section. Also, the determination of X is
described in the next section.
The discrete inductor should be selected such that the
Q of the inductor is greater than 40, and the tolerance of
the inductance is ±10% or better.
Rev. 1.3 4/06
Copyright © 2006 by Silicon Laboratories
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