AN131 Datasheet, PDF (1/16 Pages) Silicon Laboratories – The C8051F12x series is pin compatible

AN131
PORTING CONSIDERATIONS FROM ‘F02X TO ‘F12X
Relevant Devices
Clocking
This application note applies to the following devices:
C8051F020, C8051F021, C8051F022, C8051F023,
C8051F120, C8051F121, C8051F122, C8051F123,
C8051F124, C8051F125, C8051F126, and
C8051F127.
Introduction
The C8051F12x family has 128K of FLASH,
8.25K of RAM, and is capable of operating at
speeds up to 100MHz. This family is pin compati-
ble with the C8051F02x series, but due to added
flexibility and functionality, is not code compati-
ble.
This application note discusses differences between
the C8051F12x series and the C8051F02x series.
The main topics include clocking, SFR paging,
code banking, and caching. Example initialization
routines for the C8051F12x series and a checklist
to use when porting a project from a C8051F02x to
a C8051F12x device are included at the end of this
note.
Key Points
The main differences in clocking between the
C8051F02x series and the C8051F12x series
include an on-chip calibrated 24.5 MHz internal
oscillator and a phase-locked loop (PLL). When
porting code, be aware that the OSCICN register
definition has changed and a new register, CLK-
SEL, has been added to accommodate the increased
clocking flexibility.
The 24.5 MHz Internal Oscillator
The C8051F12x series has a calibrated
24.5 MHz (+/- 2%) internal oscillator, instead of
the 16 MHz (+/- 20%) internal oscillator on the
C8051F02x. On reset, the system starts operating at
a frequency of approximately 3 MHz instead of
2 MHz.
Using the PLL to achieve
operating frequencies up to
100 MHz
Operating ‘F12x devices at frequencies greater
than 30 MHz is accomplished by using the PLL to
multiply a lower frequency oscillator source.
• The C8051F12x series is pin compatible with _{The input frequency range for the PLL is 5 to}
the C8051F02x series but is not code compati- _{30 MHz and can be derived from the internal or}
ble.
external oscillator. Given a stable input signal, the
• Most of the new features in the C8051F12x
PLL output can have a wide range of frequencies
series, such as the instruction cache and code _{based on the values of PLL0MUL and PLL0DIV.}
banking registers, may be left at their default _{Keep in mind that the input clock signal is divided}
settings.
by PLL0DIV before it is fed to the phase detector.
• The ‘F12x devices implement ‘SFR Paging’. _{The phase detector input must be between 5 and}
To correctly read or write to an SFR register, _{30 MHz. The maximum output frequency of the}
the SFRPAGE register must be set to the
PLL is limited by the maximum operating fre-
correct SFR page.
quency of the device.
Rev. 1.3 12/03
Copyright © 2003 by Silicon Laboratories
AN131