1611083 Datasheet, PDF (1/4 Pages) Silicon Laboratories – This change is considered a minor change which does not affect form, fit, function, quality, or reliability.

Bulletin #1611083
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Bulletin Date: 11/8/2016
Bulletin Effective Date: 11/8/2016
Title: EFM8LB1/BB3 Datasheet Update Bulletin
Bulletin Details
Description:
Silicon Labs is pleased to announce the release of datasheet V1.0 and V1.01 for the EFM8 Laser Bee
and the EFM8 Busy Bee 3 MCUs.
The changes in the BB3 V1.0 datasheet are:
- All to be determined (TBD) values have been filled in with full characterization data.
- Added a note to clarify which DACs are available on the devices with only 2 DACs.
- Added a table on SMbus timing and operating frequency in master mode. The table details minimum
and maximum operating frequency for each class, hold times, start times, clock low and clock high
periods, and start and stop conditions.
- Added pinout information to the bootloader section to outline where the UART0 pins are located as well
as the C2 pins for each package.
- Added typical Cyclic Redundancy Check (CRC) Calculation Time for a read or write of a 256 byte block
of flash at 48 MHz.
The changes in the BB3 V1.01 datasheet are:
- Added a note in the part number table to describe and give further detail on the I-grade devices.
- Updated the QFN24 land pattern description to include the correct dimensions and openings to be used
for the center pad.
The changes to the LB1 V1.0 datasheet are:
- All to be determined (TBD) values have been filled in with full characterization data.
- Added a note to clarify which DACs are available on the devices with only 2 DACs.
- Added a table on SMbus timing and operating frequency in master mode. The table details minimum
and maximum operating frequency for each class, hold times, start times, clock low and clock high
periods, and start and stop conditions.
- Added pinout information to the bootloader section to outline where the UART0 and SMBus pins are
located as well as the C2 pins for each package.
- Added typical Cyclic Redundancy Check (CRC) Calculation Time for a read or write of a 256 byte block
of flash at 48 MHz.
The changes in the LB1 V1.01 datasheet are:
-Updated the QFN24 land pattern description to include the correct dimensions and openings to be used
for the center pad.
If you have any questions please contact your Silicon Labs representative.
Reason:
Version 1.0 EFM8LB1 Datasheet release
Version 1.01 EFM8LB1 Datasheet release
Version 1.0 EFM8BB3 Datasheet release
W7206F2 Silicon Labs Bulletin rev R
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or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 3