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1512071 Datasheet, PDF (1/6 Pages) Silicon Laboratories – This change is considered a minor change which does not affect form, fit, function, quality, or reliability.
Bulletin #1512071
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Bulletin Date: 12/7/2015
Bulletin Effective Date: 12/7/2015
Title: C8051F58x C8051F59x Rev1.3 Data Sheet
Originator: Kafai Leung
Phone: 512-532-5232
Dept: Marketing
Customer Contact: Kathy Haggar
Phone: 512-532-5261
Dept: Sales
Bulletin Details
Description:
Silicon Labs is pleased to announce that version 1.3 of the C8051F58x/59x data sheet is now available.
All items below have been included in this revision of the data sheet. The revision includes:
Power-On Reset may fail for devices shipped prior to date code 1124
- Added a note regarding an issue with /RST low time on some older devices to section 17.1 Power-On
Reset on page 153.
This issue was previously documented in the errata and has now been moved to the data sheet section
17.1 Power-On Reset on page 153. It has been removed from the errata.
Note: For devices with a date code before year 2011, work week 24 (1124), if the /RST pin is held low for
more than 1 second while power is applied to the device, and then /RST is released, a percentage of
devices may lock up and fail to execute code. Toggling the /RST pin does not clear the condition. The
condition is cleared by cycling power. Most devices that are affected will show the lock up behavior only
within a narrow range of temperatures (a 5 to 10 degrees C window). Parts with a date code of year 2011,
work week 24 (1124) or later do not have any restrictions on /RST low time. The date code of a device is
a four-digit number on the bottom-most line of each device with the format YYWW, where YY is the two-
digit calendar year and WW is the two digit work week.
Use VDD Monitor low threshold setting during normal operation
– Added the note regarding the voltage regulator and VDD monitor in the high setting from section 17.2
Power-Fail Reset/VDD Monitor on page 154 to section 10 Voltage Regulator (REG0) on page 89 and section
15.4.1 VDD Maintenance and the VDD monitor on page 143.
This note already existed in section 17 Reset Sources on page 152, and has been added to additional
locations to make it more prominent.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset
event. The output of the un-calibrated internal regulator could be below the high threshold setting of the
VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the MCU
receives a non-power on reset (POR), the MCU will remain in reset until a POR occurs (i.e., VDD Monitor
will keep the device in reset). A POR will force the VDD Monitor to the low threshold setting which is
guaranteed to be below the un-calibrated output of the internal regulator. The device will then exit reset
and resume normal operation. It is for this reason Silicon Labs strongly recommends that the VDD Monitor
is always left in the low threshold setting (i.e. default value upon POR).
W7206F2 Silicon Labs Bulletin rev N
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