S-89230BC-I8T1U Datasheet, PDF (9/24 Pages) Seiko Instruments Inc – MINI ANALOG SERIES

Rev.3.0_01
MINI ANALOG SERIES CMOS COMPARATOR
S-89230/89240 Series
 Test Circuit (Per Circuit)
1. Power supply voltage rejection ratio, input offset voltage
V_DD
 Power supply voltage rejection ratio (PSRR)
Input offset voltage (VIO)
−
+
V_IN
V_DD / 2
V_OUT
The input offset voltage (VIO) is defined as VIN − VDD / 2 when
VOUT is changed by changing VIN to VDD / 2 level. The power
supply voltage rejection ratio (PSRR) can be calculated by
following expression, with the value of VIO measured at each
VDD.
Measurement conditions:
When VDD = 1.8 V: VDD = VDD1, VIO = VIO1
When VDD = 5.0 V: VDD = VDD2, VIO = VIO2
PSRR = 20 log
V_DD1 − V_DD2
V_IO1 − V_IO2
Figure 5
2. Common-mode input signal rejection ratio, common-mode input voltage range
V_DD
 Common-mode input signal rejection ratio (CMRR)
The common-mode input signal rejection ratio (CMRR) can
be calculated by the following expression, with the offset
voltage (VIO) set as VIN1 − VIN2 after VOUT is changed by
changing VIN1.
−
Measurement conditions:
+
V_OUT
When VIN2 = VCMR Max.: VIN2 = VINH, VIO = VIO1
When VIN2 = VDD/2: VIN2 = VINL, VIO = VIO2
V_IN1
V_IN2
CMRR = 20 log
V_INH − V_INL
V_IO1− V_IO2
Figure 6
 Common-mode input voltage range (VCMR)
Varying VIN2, the range of VIN2 that satisfies the
common-mode input signal rejection ratio (CMRR) is the
common-mode input voltage range (VCMR).
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