S-8550AA-M5T1X Datasheet, PDF (9/31 Pages) Seiko Instruments Inc – RECTIFICATION, PWM CONTROL SWITCHING REGULATORS

STEP-DOWN, BUILT-IN FET, SYNCHRONOUS RECTIFICATION, PWM CONTROL SWITCHING REGULATORS
Rev.5.0_01
S-8550 Series
4. Current limit circuit
A current limit circuit is built in the S-8550 Series.
The current limit circuit monitors the current that flows in the Pch power MOS FET and limits current in order to
prevent thermal destruction of the IC due to an overload or magnetic saturation of the inductor.
When a current exceeding the current limit detection value flows in the Pch power MOS FET, the current limit
circuit operates and turns off the Pch power MOS FET since the current limit detection until one clock of the
oscillator ends. The Pch power MOS FET is turned on in the next clock and the current limit circuit resumes
current detection operation. If the value of the current that flows in the Pch power MOS FET remains the
current limit detection value or more, the current limit circuit functions again and the same operation is repeated.
Once the value of the current that flows in the Pch power MOS FET is lowered up to the specified value, the
normal operation status restores. A slight overshoot is generated in the output voltage when the current limit is
released.
The current limit detection value is fixed to 1 A (typ.) in the IC. If the time taken for the current limit to be
detected is shorter than the time required for the current limit circuit in the IC to detect, the current value that is
actually limited increases. Generally, the voltage difference between the VIN and VOUT pins is large, the
current limit detection status is reached faster and the current value increases.
5. 100% duty cycle
The S-8550 Series operates up to the maximum duty cycle at 100%. Even when the input voltage is lowered
up to the output voltage value set using the external output voltage setting resistor, the Pch power MOS FET is
kept on and current can be supplied to the load. The output voltage at this time is the input voltage from which
the voltage drop due to the direct resistance of the inductor and the on-resistance of the Pch power MOS FET
are subtracted.
6. UVLO function
The S-8550 Series includes a UVLO (under-voltage lockout) circuit to prevent the IC from malfunctioning due to
a transient status when power is applied or a momentary drop of the supply voltage. When UVLO is in the
detection state, the Pch and Nch power MOS FETs stop switching operation, and the CONT pin become Hi-Z.
Once the S-8550 Series is in the UVLO detection status, the soft-start function is reset, but the soft-start
operates by the releasing operation of UVLO after that.
Note that the other internal circuits operate normally and that the status is different from the power-off status.
The hysteresis width is set for the UVLO circuit to prevent a malfunction due to a noise that is generated in the
input voltage. A voltage about 150 mV (typ.) higher than the UVLO detection voltage is the release voltage.
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