S-8209A Datasheet, PDF (9/26 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC WITH CELL-BALANCE FUNCTION

Rev.3.4_00
BATTERY PROTECTION IC WITH CELL-BALANCE FUNCTION
S-8209A Series
 Electrical Characteristics
Table 7
(Ta = +25°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Overcharge detection
voltage
V_CU
−
V_CU − 0.025
V_CU
V_CU + 0.025 V
1
Overcharge release
voltage
V_CL
V_CL ≠ V_CU
V_CL = V_CU
Cell-balance detection
voltage
V_BU
−
V_CL − 0.05
V_CL − 0.05
V_BU − 0.025
V_CL
V_CL + 0.05
V
1
V_CL
V_CL + 0.025 V
1
V_BU
V_BU + 0.025 V
1
Cell-balance release
voltage
V_BL
Overdischarge detection
voltage
V_DL
V_BL ≠ V_BU
V_BL = V_BU
−
V_BL − 0.05
V_BL − 0.05
V_DL − 0.05
V_BL
V_BL + 0.05
V
1
V_BL
V_BL + 0.025 V
1
V_DL
V_DL + 0.05
V
1
Overdischarge release
voltage
V_DU
−
V_DU − 0.10
V_DU
V_DU + 0.10
V
1
CDT pin resistance^*1
R_CDT
V_DS = 3.5 V，V_CDT = 0 V
4.76
8.31
10.9
MΩ
2
CDT pin detection
voltage^*1
V_CDET V_DS = 3.5 V
V_DS × 0.65 V_DS × 0.70 V_DS × 0.75
V
3
Operation voltage
between VDD pin and VSS pin
V_DSOP
Output voltage
of CO pin, DO pin and CB pin fixed
1.5
−
8.0
V
−
CTLC pin H voltage
V_CTLCH V_DS = 3.5 V
V_DS × 0.55
−
V_DS × 0.90
V
4
CTLD pin H voltage
V_CTLDH V_DS = 3.5 V
V_DS × 0.55
−
V_DS × 0.90
V
4
CTLC pin L voltage
V_CTLCL V_DS = 3.5 V
V_DS × 0.10
−
V_DS × 0.45
V
4
CTLD pin L voltage
V_CTLDL V_DS = 3.5 V
V_DS × 0.10
−
V_DS × 0.45
V
4
Current consumption
during operation^*2
I_OPE
V_DS = 3.5 V
−
3.5
7.0
μA
5
Source current CTLC^*2 pin I_CTLCH V_DS = 3.5 V, V_CTLC = 0 V
320
Source current CTLD^*2 pin I_CTLDH V_DS = 3.5 V, V_CTLD = 0 V
320
400
480
nA
6
400
480
nA
6
Source current CB pin
I_CBH
V_CB = 4.0 V, V_DS = 4.5 V
30
−
−
μA
7
Sink current CB pin
I_CBL
V_CB = 0.5 V, V_DS = 3.5 V
30
−
−
μA
7
Sink current CO pin
I_COL
V_CO = 0.5 V, V_DS = 3.5 V
30
−
−
μA
7
Leakage current CO pin I_COH
V_CO = 24 V, V_DS = 4.5 V
−
−
0.1
μA
8
Sink current DO pin
I_DOL
V_DO = 0.5 V, V_DS = 3.5 V
30
−
−
μA
7
Leakage current DO pin I_DOH
V_DO = 24 V, V_DS = 1.8 V
−
−
0.1
μA
8
*1. In the S-8209A Series, users are able to set delay time for the output pins. By using the following formula, delay time is
calculated with the value of CDT pin’s resistance in the IC (R_CDT) and the value of capacitor set externally at the CDT pin
(C_CDT).
t_D [s] = −ln (1 − V_CDET / V_DS) × C_CDT [μF] × R_CDT [MΩ]
= −ln (1 − 0.7 typ.) × C_CDT [μF] × 8.31 MΩ typ.
= 10.0 MΩ typ. × C_CDT [μF]
In case of the capacitance of CDT pin C_CDT = 0.01 μF, the output pin delay time t_D is calculated by using the above
formula and as follows.
t_D [s] = 10.0 MΩ typ. × 0.01 μF = 0.1 s typ.
Test R_CDT and the CDT pin detection voltage (V_CDET) by test circuits shown in this datasheet after applying the power
supply while pulling-down the CTLC pin and the CTLD pin to the level of VSS pin outside the IC.
*2. In case of using CTLC pin and CTLD pin pulled-down to the level of VSS pin externally, the current flows into the VDD
pin (I_DD) is calculated by the following formula.
I_DD = I_OPE + I_CTLCH + I_CTLDH
Seiko Instruments Inc.
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