S19110JXXA Datasheet, PDF (8/46 Pages) Seiko Instruments Inc – FOR AUTOMOTIVE OPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-19110JxxA to S-19110RxxA Series
Rev.1.3_00
 Electrical Characteristics
1. VDD detection product
Table 7
(Ta = −40°C to +125°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1
−V_DET
3.6 V ≤ −V_DET(S) ≤ 4.15 V
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET(S)
× 0.970
−V_DET(S)
−V_DET(S)
× 1.030
V
1
−V_DET(S)
× 0.975
−V_DET(S)
−V_DET(S)
× 1.025
V
1
J / K type
3.6 V ≤ −V_DET(S) ≤ 4.15 V
+V_DET(S)
× 0.970
+V_DET(S)
+V_DET(S)
× 1.030
V
1
5.0% ≤ V_HYS ≤ 20.0%^*3
4.2 V ≤ −V_DET(S) ≤ 4.95 V
+V_DET(S)
× 0.975
+V_DET(S)
+V_DET(S)
× 1.025
V
1
Release voltage^*2
+V_DET
J / K type
3.6 V ≤ −V_DET(S) ≤ 4.15 V
+V_DET(S)
× 0.965
+V_DET(S)
+V_DET(S)
× 1.035
V
20.0% < V_HYS ≤ 30.0%^*3 _{4.2 V ≤ −VDET(S) ≤ 4.95 V}
+V_DET(S)
× 0.970
+V_DET(S)
+V_DET(S)
× 1.030
V
1
1
L / M type
V_HYS = 0%^*4
3.6 V ≤ −V_DET(S) ≤ 4.15 V
−V_DET(S)
× 0.970
−V_DET(S)
−V_DET(S)
× 1.030
V
−
4.2 V ≤ −V_DET(S) ≤ 4.95 V
−V_DET(S)
× 0.975
−V_DET(S)
−V_DET(S)
× 1.025
V
−
Current consumption I_SS
Operation voltage
V_DD
Output current
I_OUT
Leakage current
I_LEAK
Detection delay time^*6 t_RESET
Release delay time t_DELAY
CP pin discharge
ON resistance
R_CP
J / K / L / M type
V_DD = −V_DET − 0.1 V
J / K type
V_DD = +V_DET + 0.1 V
−
Output transistor
Nch
V_DS^*5 = 0.05 V
V_DD = 2.9 V, Active "L"
V_DD = 6.9 V, Active "H"
V_DD = 30.0 V, V_OUT = 30.0 V,
Output transistor Active "L"
Nch
V_DD = 2.9 V, V_OUT = 30.0 V,
Active "H"
C_N = 3.3 nF
J / K type^*7
C_P = 3.3 nF
L / M type^*8
C_P = 3.3 nF
V_DD = 6.9 V, V_CP = 0.5 V
−
0.60
−
0.60
1.8
−
0.31
−
0.45
−
−
−
−
−
8.0 10.0
8.0 10.0
8.0 10.0
0.52
−
1.60 μA 2
1.60 μA 2
36.0 V 1
− mA 3
− mA 3
2.0 μA 3
2.0 μA 3
12.0 ms 4
12.0 ms 4
12.0 ms 4
2.2 kΩ −
CN pin discharge
ON resistance
R_CN
V_DD = 2.9 V, V_CN = 0.5 V
1.0
−
5.0 kΩ −
*1. −V_DET: Actual detection voltage value, −V_DET(S): Set detection voltage value
*2. +V_DET: Actual release voltage value, +V_DET(S): Set release voltage value
*3. Although the hysteresis width can be set in the range of 5.0% to 30.0%, the release voltage accuracy differs when the
setting range exceeds 20.0%.
*4. The hysteresis width is "unavailable", so release voltage = detection voltage.
*5. V_DS: Drain-to-source voltage of the output transistor
*6. The time period from when the pulse voltage of −V_DET(S) + 0.5 V → −V_DET(S) − 0.5 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2, after the power supply voltage (V_DD) reaches the release voltage once.
*7. The time period from when the pulse voltage of +V_DET(S) − 0.5 V → +V_DET(S) + 0.5 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2.
*8. The time period from when the pulse voltage of −V_DET(S) − 0.5 V → −V_DET(S) + 0.5 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2
8