S19110AXXH Datasheet, PDF (8/49 Pages) Seiko Instruments Inc – FOR AUTOMOTIVE OPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR

FOR AUTOMOTIVE 105°C OPERATION HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
S-19110AxxH to S-19110HxxH Series
Rev.1.3_00
 Electrical Characteristics
1. VDD detection product
Table 7
(Ta = −40°C to +105°C unless otherwise specified)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
Detection voltage^*1
−V_DET 5.0 V ≤ −V_DET(S) ≤ 10.0 V
−V_DET(S)
× 0.985
−V_DET(S)
−V_DET(S)
× 1.015
V
1
A / B type
5.0% ≤ V_HYS ≤ 20.0%^*3
+V_DET(S)
× 0.985
+V_DET(S)
+V_DET(S)
× 1.015
V
1
Release voltage^*2
+V_DET
A / B type
20.0% < V_HYS ≤ 30.0%^*3
+V_DET(S)
× 0.980
+V_DET(S)
+V_DET(S)
× 1.020
V
1
C / D type
V_HYS = 0%^*4
−V_DET(S)
× 0.985
−V_DET(S)
−V_DET(S)
× 1.015
V
1
Current consumption I_SS
A / B / C / D type
V_DD = −V_DET − 0.1 V, 5.0 V ≤ −V_DET ≤ 10.0 V
A / B type
V_DD = +V_DET + 0.1 V, 5.25 V ≤ +V_DET ≤ 13.0 V
−
0.60 1.60 μA 2
−
0.60 1.60 μA 2
Operation voltage
V_DD
−
1.8
−
36.0 V
1
Output current
Output transistor _{VDD = 4.5 V, active "L"}
I_OUT
Nch
V_DS^*5 = 0.05 V
V_DD = 14.0 V, active "H"
0.5
−
0.5
−
− mA 3
− mA 3
Leakage current
I_LEAK
Output transistor
Nch
V_DD = 30.0 V, V_OUT = 30.0 V,
active "L"
V_DD = 4.5 V, V_OUT = 30.0 V,
active "H"
−
−
−
2.0 μA 3
−
2.0 μA 3
Detection delay time^*6 t_RESET
Release delay time t_DELAY
C_N = 3.3 nF
A / B type^*7
C_P = 3.3 nF
C / D type^*8
C_P = 3.3 nF
8.0 10.0 12.0 ms 4
8.0 10.0 12.0 ms 4
8.0 10.0 12.0 ms 4
CP pin discharge
ON resistance
R_CP
V_DD = 14.0 V, V_CP = 0.5 V
0.30
−
2.60 kΩ −
CN pin discharge
ON resistance
R_CN
V_DD = 4.5 V, V_CN = 0.5 V
0.63
−
2.60 kΩ −
*1. −V_DET: Actual detection voltage value, −V_DET(S): Set detection voltage value
*2. +V_DET: Actual release voltage value, +V_DET(S): Set release voltage value
*3. Although the hysteresis width can be set in the range of 5.0% to 30.0%, the release voltage accuracy differs when the
setting range exceeds 20.0%.
*4. The hysteresis width is "unavailable", so release voltage = detection voltage.
*5. V_DS: Drain-to-source voltage of the output transistor
*6. The time period from when the pulse voltage of −V_DET(S) + 1.0 V → −V_DET(S) − 1.0 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2, after the power supply voltage (V_DD) reaches the release voltage once.
*7. The time period from when the pulse voltage of +V_DET(S) − 1.0 V → +V_DET(S) + 1.0 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2.
*8. The time period from when the pulse voltage of −V_DET(S) − 1.0 V → −V_DET(S) + 1.0 V is applied to the VDD pin to when
V_OUT reaches V_DD / 2.
8