S-89210A Datasheet, PDF (7/18 Pages) Seiko Instruments Inc – MINI ANALOG SERIES CMOS COMPARATOR

Rev.2.1_00
MINI ANALOG SERIES CMOS COMPARATOR
S-89210A/89220A
„ Measurement Circuit
1. Power supply voltage rejection ratio, input offset voltage
V_DD
y Power supply voltage rejection ratio (PSRR)
Input offset voltage (V_IO)
-
+
V_DD / 2
V_IN
Figure 6
V_OUT
The input offset voltage (V_IO) is defined as V_IN − V_DD/2
when V_OUT is changed by changing V_IN to V_DD/2 level.
The power supply voltage rejection ratio (PSRR) can be
calculated by following expression, with the value of V_IO
measured at each V_DD.
Measurement conditions:
When V_DD = 1.8 V: V_DD = V_DD1, V_IO = V_IO1
When V_DD = 5.0 V: V_DD = V_DD2, V_IO = V_IO2
PSRR = 20 log
V_DD1 − V_DD2
V_IO1 − V_IO2
2. Common-mode input signal rejection ratio, common-mode input voltage range
V_DD
y Common-mode input signal rejection ratio (CMRR)
The common-mode input signal rejection ratio (CMRR)
can be calculated by the following expression, with the
offset voltage (V_IO) set as V_IN1 minus V_IN2 after V_OUT is
changed by changing V_IN1.
-
+
V_OUT
Measurement conditions:
When V_IN2 = V_CMR (max.): V_IN2 = V_INH, V_IO = V_IO1
When V_IN2 = V_DD/2: V_IN2 = V_INL, V_IO = V_IO2
V_IN1
V_IN2
CMRR = 20 log
V_INH − V_INL
V_IO1− V_IO2
y Common-mode input voltage range (V_CMR)
The common-mode input voltage range is the range
of V_IN2 in which V_OUT satisfies the common-mode input
signal rejection ratio specifications.
Figure 7
Seiko Instruments Inc.
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