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S-35392A Datasheet, PDF (7/47 Pages) Seiko Instruments Inc – 2-WIRE REAL-TIME CLOCK
Rev.1.3_00
„ AC Electrical Characteristics
Table 7 Measurement Conditions
Input pulse voltage
Input pulse rise/fall time
Output determination voltage
Output load
VIH = 0.9 × VDD, VIL = 0.1 × VDD
20 ns
VOH = 0.5 × VDD, VOL = 0.5 × VDD
100 pF + pull-up resistor 1 kΩ
2-WIRE REAL-TIME CLOCK
S-35392A
SDA
VDD
R = 1 kΩ
C = 100 pF
Remark The power supplies of the IC
and load have the same
electrical potential.
Figure 6 Output Load Circuit
Table 8 AC Electrical Characteristics
Parameter
Symbol
VDD *2 ≥ 1.3 V
Min. Typ. Max.
(Ta = −40 to +85°C)
VDD *2 ≥ 3.0 V
Unit
Min. Typ. Max.
SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time*1
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
fSCL
0
−
100
0
−
400 kHz
tLOW
4.7
−
−
1.3
−
− µs
tHIGH
4
−
−
0.6
−
− µs
tPD
−
−
3.5
−
−
0.9 µs
tSU.STA
4.7
−
−
0.6
−
−
µs
tHD.STA
4
−
−
0.6
−
−
µs
tSU.DAT
250
−
−
100
−
−
ns
tHD.DAT
0
−
−
0
−
−
µs
tSU.STO
4.7
−
−
0.6
−
− µs
tR
−
−
1
−
−
0.3 µs
tF
−
−
0.3
−
−
0.3 µs
tBUF
4.7
−
−
1.3
−
− µs
tI
−
−
100
−
−
50
ns
*1. Since the output format of the SDA pin is Nch open-drain output, SDA output delay time is determined by the values of
the load resistance (RL) and load capacity (CL) outside the IC. Therefore, use this value only as a reference value.
*2. Regarding the power supply voltage, refer to “„ Recommended Operation Conditions”.
tF
tHIGH
tLOW
tR
SCL
SDA
(Input from
S-35392A)
SDA
(Output from
S-35392A)
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tPD
Figure 7 Bus Timing
Seiko Instruments Inc.
tSU.STO
tBUF
7