S-25C256A Datasheet, PDF (20/31 Pages) Seiko Instruments Inc – Write protect function during the low power supply voltage

SPI SERIAL E²PROM
S-25C256A
Rev.2.2_02_S
 Protect Operation
Table 15 shows the block settings of Write protect. Table 16 shows the protect operation for the device. As long as bit
SRWD, the Status Register Write Disable bit, in the status register is reset to “0” (it is in reset before the shipment), the
value of status register can be changed.
These are two statues when bit SRWD is set to “1”.
• Write in the status register is possible; Write protect ( WP ) is in “H”.
• Write in the status register is impossible; Write protect ( WP ) is in “L”. Therefore the Write protect area which is set
by protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
• After setting bit SRWD, set Write protect ( WP ) to “L”.
• Set bit SRWD completed setting Write protect ( WP ) to “L”.
Figure 7 and 8 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the
status register.
By inputting “H” to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is “H”,
Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status
register (BP1, BP0) only works.
Table 15 Block Settings of Write Protect
Status Register
BP1
BP0
Area of Write Protect
Address of Write Protect Block
0
0
0%
None
0
1
25 %
6000h to 7FFFh
1
0
50 %
4000h to 7FFFh
1
1
100 %
0000h to 7FFFh
Table 16 Protect Operation
Mode
WP Pin Bit SRWD Bit WEL Write Protect Block General Block
Status Register
1
X
0
Write disable
Write disable
Write disable
Software Protect
1
X
1
Write disable
Write enable
Write enable
(SPM)
X
0
0
Write disable
Write disable
Write disable
X
0
1
Write disable
Write enable
Write enable
Hardware Protect
0
1
0
Write disable
Write disable
Write disable
(HPM)
0
1
1
Write disable
Write enable
Write disable
Remark X = Don’t care
20