S-19104N10H-M5T1U Datasheet, PDF (20/40 Pages) Seiko Instruments Inc – VOLTAGE DETECTOR WITH SENSE PIN

FOR AUTOMOTIVE 105°C OPERATION BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN
S-19104/19106 Series
Rev.1.2_00
2. 5 Malfunction when V_DD falls
As seen in Figure 27, note that if the VDD pin voltage (V_DD) drops steeply below 1.2 V when −V_DET < V_SENSE <
+V_DET, erroneous detection may occur.
When V_{DD_Low} ≥ 1.2 V, erroneous detection does not occur.
When V_{DD_Low} < 1.2 V, the more the V_DD falling amplitude increases or the shorter the falling time becomes, the
easier the erroneous detection.
Perform thorough evaluation in actual application.
V_DD
V_{DD_High}
V_{DD_Low} (Voltage drops below 1.2 V.)
V_SENSE
+V_DET
−V_DET
V_OUT
V_OUT falling influenced by V_DD falling
(erroneous detection)
Figure 27
The S-19104C50 example in Figure 28 shows an example of erroneous detection boundary conditions.
Remark
12
10
8
Danger of erroneous
6
detection
4
2
0
0.1
1
10
100 1000
tF [s]
Figure 28
Test conditions
Product name: S-19104C50
V_SENSE:
−V_DET(S) + 0.1 V
V_{DD_High}:
VDD pin voltage before falling
V_{DD_Low}:
VDD pin voltage after falling (0.95 V)
ΔV_DD:
V_{DD_High} − V_{DD_Low}
t_F:
Falling time of V_DD from V_{DD_High} − ΔV_DD × 10% to V_{DD_Low} + ΔV_DD × 10%
VDD_High
VDD_High  VDD  10%
VDD
VDD_Low  VDD  10%
VDD_Low
tF
Figure 29
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