S1002 Datasheet, PDF (19/39 Pages) Seiko Instruments Inc – VOLTAGE DETECTOR WITH SENSE PIN

Rev.1.1_00
VOLTAGE DETECTOR WITH SENSE PIN
S-1002 Series
2. 3 Power on sequence
Apply power in the order, the VDD pin then the SENSE pin.
As seen in Figure 26, when V_SENSE ≥ +V_DET, the OUT pin output (V_OUT) rises and the S-1002 Series becomes the
release status (normal operation).
V_DD
V_SENSE
+V_DET
V_OUT
t_RESET
Figure 26
Caution If power is applied in the order the SENSE pin then the VDD pin, an erroneous release may occur
even if V_SENSE < +V_DET.
2. 4 Precautions when shorting between the VDD pin and the SENSE pin
2. 4. 1 Input resistor
Do not connect the input resistor (R_A) when shorting between the VDD pin and the SENSE pin.
A feed-through current flows through the VDD pin at the time of release. When connecting the circuit shown as
Figure 27, the feed-through current of the VDD pin flowing through R_A will cause a drop in V_SENSE at the time of
release.
At that time, oscillation may occur if V_SENSE ≤ −V_DET.
R_A
V_DD
VDD
SENSE
OUT
VSS
Figure 27
2. 4. 2 Parasitic resistance and parasitic capacitance
Due to the difference in parasitic resistance and parasitic capacitance of the VDD pin and the SENSE pin,
power may be applied to the SENSE pin first.
Note that an erroneous release may occur if this happens (refer to "2. 3 Power on sequence").
Caution
In CMOS output product, make sure that the VDD pin input impedance does not become too
high, regardless of the above. Since a feed-through current is large, a malfunction may occur if
the VDD pin voltage changes greatly at the time of release.
Seiko Instruments Inc.
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