S-93A46A Datasheet, PDF (15/34 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

Rev.2.1_00
CMOS SERIAL E²PROM
S-93A46A/56A/66A
4.5 Erasing Chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and
then input the ERAL instruction and an address following the start bit. Any address can be input.
There is no need to input data. The chips erase operation starts when CS goes low. When the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the ERAL
instruction. For details of the clock pulse monitoring circuit, refer to “„ Function to Protect Against
Write due to Erroneous Instruction Recognition”.
CS
t CDS
SK
1
2
3
4
5
6
7
89
Verify
Standby
DI
<1> 0
010
DO
4Xs
t SV
t HZ1
Busy _Ready
Hi-Z
tPR
Figure 12 Chip Erase Timing (S-93A46A)
CS
t CDS
SK
1 2 3 4 5 6 7 8 9 10 11
Verify
Standby
DI
<1> 0
010
6Xs
DO
tSV
Busy _Ready
tPR
t HZ1
Hi-Z
Figure 13 Chip Erase Timing (S-93A56A/66A)
Seiko Instruments Inc.
15