S-1721 Datasheet, PDF (15/38 Pages) Seiko Instruments Inc – SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.1.1_00
S-1721 Series
„ Standard Circuit
INPUT
C_IN^*1
VIN
VOUT1
ON/OFF1 _VOUT2
ON/OFF2
VSS
C_L2^*2
OUTPUT 1
OUTPUT 2
C_L1^*2
Single GND
GND
*1. C_IN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 1.0 µF or more can be used for C_L1 and C_L2.
Figure 21
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
„ Condition of Application
Input capacitor (C_IN) :
Output capacitor (C_L1, C_L2) :
1.0 µF or more
1.0 µF or more (ceramic capacitor)
Caution A general series regulator may oscillate, depending on the external components. Confirm that no
oscillation occurs in the application for which the above capacitors are used.
„ Selection of Input and Output Capacitors (C_IN, C_L1, C_L2)
The S-1721 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 1.0 µF or more over the entire temperature range.
When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, the capacitance must be 1.0 µF or
more.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended capacitance for an application is C_IN ≥ 1.0 µF, C_L1 ≥ 1.0 µF, C_L2 ≥ 1.0 µF; however, when selecting
the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual
device.
Seiko Instruments Inc.
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