S1212B Datasheet, PDF (14/58 Pages) Seiko Instruments Inc – HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1212B/D Series
Rev.3.0_00
 Operation
1. Basic operation
Figure 15 shows the block diagram of the S-1212B/D Series to describe the basic operation.
The error amplifier compares the feedback voltage (V_fb) whose output voltage (V_OUT) is divided by the feedback
resistors (R_s and R_f) with the reference voltage (V_ref). The error amplifier controls the output transistor, consequently,
the regulator starts the operation that holds V_OUT constant without the influence of the input voltage (V_IN).
VIN
Current
supply
V_ref
Error amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 15
2. Output transistor
In the S-1212B/D Series, a low on-resistance P-channel MOS FET is used between the VIN pin and the VOUT pin as
the output transistor. In order to hold V_OUT constant, the on-resistance of the output transistor varies appropriately
according to the output current (I_OUT).
Caution Since a parasitic diode exists between the VIN pin and the VOUT pin due to the structure of the
transistor, the IC may be damaged by a reverse current if V_OUT becomes higher than V_IN.
Therefore, be sure that V_OUT does not exceed V_IN + 0.3 V.
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