S11L10 Datasheet, PDF (14/35 Pages) Seiko Instruments Inc – SUPER-LOW OUTPUT VOLTAGE LOW DROPOUT

SUPER-LOW OUTPUT VOLTAGE LOW DROPOUT CMOS VOLTAGE REGULATOR
S-11L10 Series
Rev.2.2_00
 Operation
1. Basic operation
Figure 13 shows the block diagram of the S-11L10 Series.
The error amplifier compares the reference voltage (V_ref) with feedback voltage (V_fb), which is the output voltage
resistance-divided by feedback resistors (R_s and R_f). It supplies the gate voltage necessary to maintain the constant
output voltage which is not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
Vref
Error
amplifier
−
+
Reference voltage
circuit
*1
Rf
Vfb
Rs
VOUT
VSS
*1. Parasitic diode
Figure 13
2. Output transistor
In the S-11L10 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to reverse
current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of V_OUT became
higher than V_IN.
14
Seiko Instruments Inc.