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S7760A Datasheet, PDF (13/54 Pages) Seiko Instruments Inc – PROGRAMMABLE PORT CONTROLLER (PORT EXPANDER WITH BUILT-IN E2PROM CIRCUIT) | |||
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PROGRAMMABLE PORT CONTROLLER (PORT EXPANDER WITH BUILT-IN E2PROM CIRCUIT)
Rev.2.0_01
S-7760A
ï® Command
1. Reload
This is a 1-byte command. Users can reload by inputting either of R / W in 0/1. When inputting this command, the
data corresponding to the E2PROM is loaded to the register. After completing reload, (if the condition is satisfied), the
timer action starts. The reload command is not accepted during the timer action (from its start to the final invert of
output). Refer to âï® Condition to Start Timerâ regarding details.
2. Switching access to register/E2PROM
This is a 1-byte command. The mode is in âregister access modeâ when this command is R / W = 0, âE2PROM
access modeâ when this command is R / W = 1. The register corresponding to the E2PROM is the one to be
reloaded. In register access mode, only the register is rewritten, the E2PROM maintains the prior data. In âE2PROM
access modeâ, both data in the register and E2PROM is rewritten.
3. Timer enable register
A timer enable register is a 4-bit register for Write only (it sends back FFh during Read). By setting each bit in the
register in â1â, an oscillation circuit starts, output from the lower 4ch ports (DO3 to 0) invert after the elapsed period
which is set by a timer setting register. This action is called âtimer actionâ. This timer action starts at the point when
receiving TEN0 which is LSB in the register. The bit automatically goes back in â0â after writing â1â in the timer enable
register. Users cannot write in this register during the timer action (from the start to the final invert of output). This
register is not the one to be reloaded, thus it does not have the data which corresponds to the E2PROM. The option is
available for the condition to start a timer; Condition AND with TIMEN = High, depending on the option. Refer to âï®
Condition to Start Timerâ regarding details.
B7
B6
B5
MSB
ï¼
ï¼
ï¼
B4
B3
B2
B1
B0
ï¼
TEN 3 TEN 2 TEN 1 TEN 0
LSB
W
W
W
W
W
W
W
W
0 : Disable to invert output
1 : Enable to invert output
Figure 14 Timer Enable Register
13
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