S-35720C01A-K8T2U Datasheet, PDF (13/21 Pages) Seiko Instruments Inc – Low current consumption

FOR AUTOMOTIVE 125°C OPERATION WITH INTERRUPT TIME SETTING PIN CONVENIENCE TIMER
Rev.1.1_00
S-35720 Series
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 Chattering Elimination of RST Pin
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The RST pin has a built-in chattering elimination circuit, and the output logic is active "L".
Figure 15 is a timing chart of chattering elimination. Perform sampling at 8 Hz and operate the shift register circuit.
Perform the shift operation for 3 times, and reset the counter when DF1 to DF3 are all "L". During the charttering
_^e_^l_ⁱ_^m__ⁱ_^{nation, the pulse width, 2 per}__^io__^d__^s_ ^{(approximately 0.25 seconds) of clock (8 Hz), can be eliminated. To determine the}
RST pin "L" input, maintain the R_{___}S_{__}T_{__} pin "L" input during the perio_{_}d_{___}l_{_}o_{_}n_{_} ger than 3.5 periods (0.438 seconds) of clock (8
Hz). Similarly, to determine the RST pin "H" input, maintain the RST pin "H" input during the period longer than 3.5
periods (0.438 seconds) of clock (8 Hz).
Clock (8 Hz)
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RST pin input signal
Shift register_DF1
Shift register _DF2
Shift register _DF3
Reset signal after
chattering elimination
Chattering elimination width
2 periods
Count-up action starts
3.5 periods
3.5 periods
Counter reset
Figure 15 Timing Chart of Chattering Elimination
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