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S-25A080A Datasheet, PDF (13/31 Pages) Seiko Instruments Inc – 125°C OPERATION SPI SERIAL E2PROM | |||
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125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
 Operation
1. Status register
The status registerâs organization is below. The status register can Write and Read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch
Write In Progress
Figure 8 Organization of Status Register
The status/control bits of the status register are as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = â1â, WP = âLâ), this device goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be
performed.
1. 2 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile bit. The area size of Software Protect against WRITE instruction
is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against
the WRITE instruction, set either or both of bit BP1 and BP0 to â1â. Rewriting bit BP1 and BP0 is possible unless
they are in Hardware Protect mode. Refer to â Protect Operationâ for details of âBlock Protectâ.
1. 3 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
â1â, this is the status that Write Enable Latch is set. If bit WEL is â0â, Write Enable Latch is in reset, so that the S-
25A080A/160A/320A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
⢠The power supply voltage is dropping
⢠Power-on
⢠After performing WRDI
⢠After the Write operation by the WRSR instruction
⢠After the Write operation by the WRITE instruction
Seiko Instruments Inc.
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