S-1155 Datasheet, PDF (13/28 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

Rev.1.1_00
HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1155 Series
„ Operation
1. Basic operation
Figure 11 shows the block diagram of the S-1155 Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-divided by
feedback resistors R_s and R_f. It supplies the gate voltage necessary to maintain the constant output voltage which
is not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
V_ref
Error amplifier
−
+
*1
R_f
VOUT
V_fb
Reference voltage
circuit
R_s
VSS
*1. Parasitic diode
Figure 11
2. Output transistor
In the S-1155 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due to inverse
current which flows, because of a parasitic diode between the VIN and VOUT pin, when the potential of V_OUT
became higher than V_IN.
Seiko Instruments Inc.
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