S-1142C Datasheet, PDF (13/32 Pages) Seiko Instruments Inc – HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR

HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.1.2_01
S-1142C/D Series
 Operation
1. Basic operation
Figure 11 shows the block diagram of the S-1142C/D Series.
The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage
resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the
constant output voltage which is not influenced by the input voltage and temperature change, to the output
transistor.
VIN
Current
supply
V_ref
Error amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 11
2. Output transistor
In the S-1142C/D Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to
reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT
became higher than VIN.
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