S-L2985 Datasheet, PDF (12/23 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION WLP PACKAGE LOW DROPOUT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION WLP PACKAGE LOW DROPOUT CMOS VOLTAGE REGULATOR
S-L2985 Series
Rev.2.1_00
3. Shutdown pin (ON/OFF pin)
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-
in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially
reduce the current consumption. The VOUT pin becomes the V_SS level due to the internally divided
resistance of several MΩ between the VOUT pin and VSS pin.
The structure of the ON/OFF pin is as shown in Figure 12. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption
increases if a voltage of 0.3 V to V_IN – 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not
used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.
Table 5
Logic Type
A
A
B
B
ON/OFF Pin
“L”: Power on
“H”: Power off
“L”: Power off
“H”: Power on
Internal Circuits
Operating
Stopped
Stopped
Operating
VOUT Pin Voltage
Set value
V_SS level
V_SS level
Set value
Current Consumption
I_SS1
I_SS2
I_SS2
I_SS1
VIN
ON/OFF
VSS
Figure 12
„ Selection of Output Capacitor (C_L)
The S-L2985 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. A
ceramic capacitor with a capacitance of 0.47 μF or more can be used. Even if using an OS capacitor, tantalum
capacitor, or aluminum electrolytic capacitor, a capacitance of 0.47 μF or more and an ESR of 10 Ω or less are
required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor.
When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
12
Seiko Instruments Inc.