S-8533 Datasheet, PDF (12/31 Pages) Seiko Instruments Inc – STEP-DOWN, SYNCHRONOUS PWM CONTROL SWITCHING REGULATOR CONTROLLER

STEP-DOWN, SYNCHRONOUS PWM CONTROL SWITCHING REGULATOR CONTROLLER
S-8533 Series
Rev.2.3_00
3. External Transistor
Enhancement (P-channel, N-channel) MOS FETs can be used as external switching transistors for the S-8533
Series.
3. 1 Enhancement (P-channel, N-channel) MOS FET
The PDRV/NDRV pin of the S-8533 Series is capable of directly driving a P-channel or N-channel MOS FET with a
gate capacity around 1000 pF.
When P-channel/N-channel MOS FETs are chosen, efficiency will be 2 to 3% higher than that achieved by a
PNP/NPN bipolar transistor since MOS FET switching speeds are higher than PNP/NPN bipolar transistors and
power dissipation due to the base current is avoided.
The important parameters in selecting MOS FETs include the threshold voltage, breakdown voltage between gate
and source, breakdown voltage between drain and source, total gate capacity, on-resistance, and the current
ratings.
The PDRV and NDRV pins swing from voltage V_IN over to voltage V_SS. If the input voltage is low, a MOS FET with a
low threshold voltage has to be used so that the MOS FET will turn on as required. If, conversely, the input voltage
is high, select a MOS FET whose gate-source breakdown voltage is higher than the input voltage by at least several
volts.
Immediately after the power is turned on, or when the power is turned off (that is, when the step-down operation is
terminated), the input voltage will be imposed across the drain and the source of the MOS FET. The transistor
therefore needs to have drain-source breakdown voltage that is also several volts higher than the input voltage.
The total gate capacity and the on-resistance affect the efficiency.
The power dissipation for charging and discharging the gate capacity by switching operation will affect the efficiency
especially at low load current region when the total gate capacity becomes larger and the input voltage becomes
higher. If the efficiency under light loads is a matter of particular concern, select a MOS FET with a small total gate
capacity.
In regions where the load current is high, the efficiency is affected by power dissipation caused by the on-resistance
of the MOS FET. If the efficiency under heavy loads is particularly important in the application, choose a MOS FET
with as low an on-resistance as possible.
As for the current rating, select a MOS FET whose maximum continuous drain current rating is higher than I_PK.
If an external P-channel MOS FET has much different characteristics (input capacitance, threshold value, etc.) from
an external N-channel MOS FET, they turn ON at the same time, flowing a through current and reducing efficiency.
If a MOS FET with a large input capacitance is used, switching dissipation increases and efficiency decreases. If it
is used at several hundreds of mA or more, the dissipation at the MOS FET increases and may exceed the
permissible dissipation of the MOS FET. To select P-channel and N-channel MOS FETs, evaluate the performance
by testing under the actual condition.
Caution If the load current is large, the P-channel MOS FET dissipation increases and heat is generated.
Pay attention to dissipate heat from the P-channel MOS FET.
Efficiency data using Sanyo Electric Co., Ltd. CPH6303, CPH6403, and Vishay Siliconix Si3441DV and Si3442DV
for applications with an input voltage range of 6 to 8 V or less is included for reference. For applications with an
input voltage range of 6 to 8 V or more, efficiency data using Sanyo Electric Co., Ltd. CPH6302, CHP6402, and
Vishay Siliconix Si3454DV and Si3455DV is included. Refer to “„ Reference Data”.
Current flow in the parasitic diode is not allowed in some MOS FETs. In this case, a Schottky diode must be
connected in parallel to the MOS FET. The Schottky diode must have a low forward voltage, a high switching
speed, a reverse-direction withstand voltage of V_IN or higher, and a current rating of I_PK or higher.
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Seiko Instruments Inc.