S-818_1 Datasheet, PDF (12/32 Pages) Seiko Instruments Inc – LOW DROPOUT CMOS VOLTAGE REGULATOR

LOW DROPOUT CMOS VOLTAGE REGULATOR
S-818 Series
Rev.2.1_00
„ Operation
1. Basic Operation
Figure 12 shows the block diagram of the S-818 Series.
The error amplifier compares a reference voltage (V_ref) with the part of the output voltage divided by the
feedback resistors R_s and R_f. It supplies the output transistor with the gate voltage, necessary to ensure
certain output voltage free of any fluctuations of input voltage and temperature.
VIN
Current source
V_ref
Error amplifier
−
+
*1
R_f
VOUT
Reference
voltage circuit
R_S
VSS
*1. Parasitic diode
Figure 12 Block diagram
2. Output Transistor
The S-818 Series uses a Pch MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN+0.3 V to prevent the voltage regulator from being damaged due to
inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
12
Seiko Instruments Inc.