S-25C160A Datasheet, PDF (12/39 Pages) Seiko Instruments Inc – Write protect function during the low power supply

SPI SERIAL E²PROM
S-25C160A
Rev.4.2_02_H
 Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
b7
b6
b5
b4
b3
b2
b1
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect
Write Enable Latch
Write In Progress
Figure 11 Organization of Status Register
The status / control bits of the status register as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = “1”, WP = “L”), this device goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be
performed.
1. 2 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area
against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible
unless they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”.
1. 3 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the
device does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the Write operation by the WRSR instruction has completed
• After the Write operation by the WRITE instruction has completed
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