S-1206 Datasheet, PDF (12/36 Pages) Seiko Instruments Inc – ULTRA LOW CURRENT CONSUMPTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

ULTRA LOW CURRENT CONSUMPTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1206 Series
Rev.1.1_00
„ Operation
1. Basic Operation
Figure 11 shows the block diagram of the S-1206 Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-divided by
feedback resistors R_s and R_f. It supplies the output transistor with the gate voltage necessary to ensure a certain
output voltage free of any fluctuations of input voltage and temperature.
VIN
Constant
current supply
V_ref
Error amplifier
−
+
*1
R_f
VOUT
V_fb
Reference voltage
circuit
R_s
VSS
*1. Parasitic diode
Figure 11
2. Output Transistor
The S-1206 Series uses a low-on-resistance P-channel MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the IC from being damaged due to inverse current flowing
from the VOUT pin through a parasitic diode to the VIN pin.
12
Seiko Instruments Inc.