S1170 Datasheet, PDF (11/30 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION AND LOW DROPOUT

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Rev.4.1_00
S-1170 Series
 Standard Circuit
Input
C_IN^*1
VIN VOUT
ON/OFF
VSS
Output
C_L^*2
Single GND
GND
*1. C_IN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 4.7 μF or more can be used for C_L.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
 Condition of Application
Input capacitor (C_IN):
Output capacitor (C_L):
ESR of output capacitor:
4.7 μF or more
4.7 μF or more
0.5 Ω or less
Caution Generally a series regulator may cause oscillation, depending on the selection of external
parts. Check that no oscillation occurs with the application using the above capacitor.
 Selection of Input and Output Capacitors (C_IN, C_L)
The S-1170 Series requires an output capacitor between the VOUT pin and the VSS pin for phase
compensation. A ceramic capacitor with a capacitance of 4.7 μF or more provides a stable operation in all
temperature ranges. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic
capacitor, the capacitance must be 4.7 μF or more, and the ESR must be 0.5 Ω or less.
The output overshoot and undershoot values, which are transient response characteristics, vary depending
on the output capacitor value. The required capacitance value for the input capacitor differs depending on
the application.
The recommended value for an application is C_IN ≥ 4.7 μF and C_L ≥ 4.7 μF, however, perform a thorough
evaluation using the actual device, including evaluation of temperature characteristics.
Seiko Instruments Inc.
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