S93A86A Datasheet, PDF (10/39 Pages) Seiko Instruments Inc – 125C OPERATION 3-WIRE SERIAL

125°C OPERATION 3-WIRE SERIAL E²PROM FOR AUTOMOTIVE
S-93A86A
Rev.6.1_00
 Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during t_CDS. While a
low level is being input to CS, the S-93A86A is in standby mode, so the SK and DI inputs are invalid and no instructions
are allowed.
 Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit is
not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial memory
operation. For example, when the CPU instruction set is 16 bits, the number of instruction set clocks can be
adjusted by inserting the 3-bit dummy clock in S-93A86A.
2. Start bit input failure
• When the output status of the DO pin is high during the verify period after a write operation, if a high level is input to
the DI pin at the rising edge of SK, the S-93A86A recognizes that a start bit has been input. To prevent this
failure, input a low level to the DI pin during the verify operation period (Refer to “4. 1 Verify operation”).
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the data
output from the CPU and the serial memory collide may be generated, preventing successful input of the start bit.
Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
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Seiko Instruments Inc.