S-19101C25H-M5T2U Datasheet, PDF (10/31 Pages) Seiko Instruments Inc – BUILT-IN DELAY CIRCUIT

FOR AUTOMOTIVE 105°C OPERATION VOLTAGE DETECTOR BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
S-19101xxxH Series
Rev.1.0_01
 Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (+VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). At this time, as shown in Figure 13, the comparator input voltage
is
(RB + RC ) •
RA + RB +
VDD
RC
.
(2) When VDD decreases to −VDET or less (point A in Figure 14), the Nch transistor is ON and the Pch transistor
is OFF so that VSS is output.
(3) The output is indefinite by decreasing VDD to the IC’s minimum operation voltage or less. If the output is
pulled up, it will be VDD.
(4) VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD is less than +VDET,
the output is VSS.
(5) When increasing VDD to +VDET or more (point B in Figure 14), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VDD
VSS
R_A
+
*1
−
R_B
V_REF
R_C
*1
Delay _Pch
circuit
OUT
*1
Nch
*1
CD
C_D
*1. Parasitic diode
Figure 13 Operation 1
(1) (2) (3) (4)
A
B
Detection voltage (−V_DET)
(5)
V_DD
Release voltage (+V_DET)
Minimum operation voltage
VSS
V_DD
Output from OUT pin
V_SS
t_D
Remark The release voltage is set to the same value as the detection voltage, since there no hysteresis width.
Figure 14 Operation 2
10