AATIAN70 Datasheet, PDF (9/10 Pages) SiGe Semiconductor, Inc. – CMOS Low Voltage LDO Linear Regulator

EV-137
AAT3244 EVAL: 300mA Adjustable Dual
CMOS Low Voltage LDO Linear Regulator
Test: PSRR vs. Frequency
1. Configure the specified test equipment as shown in Figure 8.
2. Enable dual LDO by setting JP1 and JP3 to the ‘ON’ position, as shown in Figure 2. Connect both inputs
of UUT to V_CC by JP2 and JP4 as shown in Figure 2.
3. Connect the SOURCE OUT, CHA from the Network Analyzer to the input of the LDO, and CHB to the out-
put of the LDO.
4. Set the output load current to 10mA (light load).
5. Sweep the frequency from SOURCE OUT of the Network Analyzer from 10Hz to 1MHz, while monitoring
the sine waves from the input and the output of the LDO.
PSRR(dB)
=
abs
⎛⎝₂₀
·
log
V_OUT (AC)⎞
V_IN (AC) ⎠
Figure 8: AAT3244 Evaluation Board Connection Diagram for PSRR.
EV-137.2007.08.1.0
9