PSB21911 Datasheet, PDF (78/164 Pages) Siemens Semiconductor Group – ISDN Echocancellation Circuit for Terminal Applications IEC-Q TE

PSB 21911
PSF 21911
U-Transceiver
2.5.10 Analog Line Port
The analog part of the IEC-Q TE consists of three main building blocks:
– The analog-to-digital converter in the receive path
– The digital-to-analog converter in the transmit path
– The output buffer in the transmit path
Furthermore it contains some special functions. These are:
– Analog test loop-back
– Level detect function
Analog-to-Digital Converter
The ADC is a sigma-delta modulator of second order using a clock rate of 15.36-MHz.
The peak input signal measured between AIN and BIN must be below 4 Vpp. In case the
signal input is too low (long range), the received signal is amplified internally by 6 dB.
The maximum signal to noise ratio is achieved with 1.3 Vpp (long range) and 2.6 Vpp
(short range) input signal voltage.
Digital-to-Analog Converter
The output pulse is shaped by a special DAC. The DAC was optimized for excellent
matching between positive and negative pulses and high linearity. It uses a fully
differential capacitor approach. The staircase-like output signal of the DAC drives the
output buffers. The shape of a DAC-output signal is shown below, the peak amplitude is
normalized to one. This signal is fed to an RC-lowpass of first order with a corner
frequency of 1 MHz ± 50%.
The duration of each pulse is 24 steps, with T0 = 0.78 µs per step. On the other hand,
the pulse rate is 80-kHz or one pulse per 16 steps. Thus, the subsequent pulses are
overlapping for a duration of 8 steps.
Semiconductor Group
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11.97