HYM328020S Datasheet, PDF (7/10 Pages) Siemens Semiconductor Group – 8M x 32-Bit Dynamic RAM Module

HYM 328020S/GS-50/-60
8M × 32-Bit
AC Characteristics ⁵⁾⁶⁾
T_A = 0 to 70 °C,V_CC = 5 V ± 10 %, t_T = 5 ns
Parameter
common parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
Symbol
Limit Values
Unit
-50
-60
min. max. min. max.
t_RC
90 –
110 –
ns
t_RP
30 –
40 –
ns
t_RAS
50 10k 60 10k ns
t_CAS
13 10k 15 10k ns
t_ASR
0
–
0
–
ns
t_RAH
8
–
10 –
ns
t_ASC
0
–
0
–
ns
t_CAH
10 –
15 –
ns
t_RCD
18
37
20
45
t_RAD
13 25 15
30 ns
t_RSH
13
15 –
ns
t_CSH
50
60 –
ns
t_CRP
5
–
5
–
ns
t_T
3
50 3
50 ns
t_REF
–
32 –
32 ms
Note
7
Read Cycle
Access time from RAS
t_RAC
–
50 –
60 ns 8, 9
Access time from CAS
t_CAC
–
13 –
15 ns 8, 9
Access time from column address
t_AA
–
25 –
30 ns 8,10
Column address to RAS lead time
t_RAL
25 –
30 –
ns
Read command setup time
t_RCS
0
–
0
–
ns
Read command hold time
t_RCH
0
–
0
–
ns 11
Read command hold time referenced to
t_RRH
0
–
0
–
ns 11
RAS
CAS to output in low-Z
Output buffer turn-off delay
t_CLZ
0
t_OFF
0
–
0
13 0
–
ns 8
15 ns 12
Semiconductor Group
7