C167SR Datasheet, PDF (63/66 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

C167SR
CLKOUT
ALE
Running cycle ¹⁾
t₃₂
t₃₃
t₃₀
t₃₄
t₃₁
READY
waitstate
MUX/Tristate ⁶⁾
t₂₉
7)
Command
RD, WR
Sync
READY
Async
READY
2)
t₃₅
t₃₆
t₅₈
t₅₉
3)
3)
t₅₈
t₅₉
3)
5) ^t37
Figure 16
CLKOUT and READY
t₃₅
t₃₆
3)
t₆₀ ⁴⁾
see 6)
Notes
1) _{Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).}
2) _{The leading edge of the respective command depends on RW-delay.}
3) _{READY sampled HIGH at this sampling point generates a READY controlled waitstate,}
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4) _{READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or}
WR).
5) _{If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT}
(eg. because CLKOUT is not enabled), it must fulfill t₃₇ in order to be safely synchronized. This is guaranteed,
if READY is removed in reponse to the command (see Note ⁴⁾).
6) _{Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may}
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7) _{The next external bus cycle may start here.}
Semiconductor Group
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