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TDA4605 Datasheet, PDF (6/21 Pages) STMicroelectronics – CONTROL CIRCUIT FOR SWITCH MODE POWER SUPPLIES USING MOS TRANSISTORS
TDA 4605
Block Diagram
Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is ted to the stop comparator.
Pin 2
A voltage proportional to the drain current ot the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulating amplifier, the logic is reset by the stop comparator
and consequently the output ot pin 5 is switched to low potential. Further inputs tor the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage monitor.
Pin 3
The down-divide primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a leved suitable for MOS-
power transistors.
Pin 6
From the supply voltage V6 are derived a stable internal reference VREF and the switching threshold
V6A , V6E , V6 max and V6 min for the supply voltage monitor. All reference values (VR , V2B , VST) are
derived from VREF . If V6 > VVE the VREF is switched on and switched off when V6 < V6A . In addition,
the logic is released only for V6 min < V6 < V6 max .
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.
Semiconductor Group
38