SDA9253 Datasheet, PDF (5/25 Pages) Siemens Semiconductor Group – 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM)

SDA 9253
Typical Memory Cycle Sequence
A typical application of the TV-SAM is a real-time interfield image processing combined with flicker
reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via
port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle
of 4 consecutive RE cycles of transfer is needed:
1st. RE-cycle: Read transfer from memory to latch A
2nd. RE-cycle: Read transfer from memory to latch B
3rd. RE-cycle: Same as 1st. RE cycle
4th. RE-cycle: Write transfer from latch C to memory
Each transfer cycle is preceeded by an address cycle as shown in the diagram page 6:
For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at
port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we
have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must
be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx.
296 ns is necessary.
The beginning of a block of 16 serial data at port A or B is determined by RA and RB, respectively.
The end of the serial input data block at port C is controlled by WT. Since RA, RB and WT can be
independently chosen (except for small forbidden time windows when memory transfers are
executed), the serial data streams can be shifted against each other without influencing the RE
cycles.
Semiconductor Group
5
1998-01-30