C163-L Datasheet, PDF (42/68 Pages) Siemens Semiconductor Group – 16-bit CMOS Single-Chip Microcontroller

11Aug98@14:48h Intermediate Version
C163-L
Parameter
Symbol
Max. CPU Clock
= 25 MHz
min.
max.
Address hold after RD, WR t₂₇
ALE falling edge to CS
t₃₈
CS low to Valid Data In t₃₉
CC 26 + t_F
CC -4 - t_A
SR –
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
t₄₀ CC 46 + t_F
t₄₂ CC 16 + t_A
–
10 - t_A
40
+ t_C + 2t_A
–
–
ALE fall. edge to RdCS, t₄₃ CC -4 + t_A
–
WrCS (no RW delay)
Address float after RdCS, t₄₄ CC –
0
WrCS (with RW delay)
Address float after RdCS, t₄₅ CC –
20
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
t₄₆ SR –
16 + t_C
RdCS to Valid Data In
(no RW delay)
t₄₇ SR –
36 + t_C
RdCS, WrCS Low Time t₄₈ CC 30 + t_C –
(with RW delay)
RdCS, WrCS Low Time t₄₉ CC 50 + t_C –
(no RW delay)
Data valid to WrCS
t₅₀ CC 26 + t_C
–
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
t₅₁ SR 0
t₅₂ SR –
t₅₄ CC 20 + t_F
t₅₆ CC 20 + t_F
–
20 + t_F
–
–
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
min.
max.
2TCL - 14 + t_F –
-4 - t_A
10 - t_A
–
3TCL - 20
+ t_C + 2t_A
3TCL - 14 + t_F –
TCL - 4
–
+ t_A
-4
–
+ t_A
–
0
Unit
ns
ns
ns
ns
ns
ns
ns
–
TCL
ns
–
2TCL - 24 ns
+ t_C
–
3TCL - 24 ns
+ t_C
2TCL - 10 –
ns
+ t_C
3TCL - 10 –
ns
+ t_C
2TCL - 14 –
ns
+ t_C
0
–
ns
–
2TCL - 20 + t_F ns
2TCL - 20 + t_F –
ns
2TCL - 20 + t_F –
ns
Semiconductor Group
40
1998-08