PSB7230 Datasheet, PDF (36/179 Pages) Siemens Semiconductor Group – Joint Audio Decoder-Encoder for Analog Videophone JADE AN

PSB 7230
Interfaces and Memory Organization
3.3
Directly Accessible Register Bank
3.3.1 Input/Output Registers
This area contains the locations for receiving/transmitting real-time audio and data
between the serial interfaces (IOM-2 and Serial Audio Interface) and the Host (or
embedded DSP).
The PSB 7230 implements one receive and one transmit audio channel, denoted RC1
and XC1, respectively. Further, one receive and one transmit channel is provided to
access the serial data receiver input data and the serial data transmitter output,
respectively, called HR1 and HX1.
Transfer of audio samples is interrupt supported, whereby two possibilities are provided:
– interrupt status generated after a programmable number of bits (1 … 32) have been
shifted in/out;
– interrupt indicating the start of a physical frame (normally at 8 kHz, either from FSC,
RFS or TFS frame sync pulses): in this case the number of significant bits depends
on the time-slot length programmed for that channel on the line (DU/DD/SR/ST).
The interrupt statuses may generate a maskable interrupt on the high priority interrupt
lines INTR (Host) and/or INT0 (embedded DSP), respectively.
RC1, XC1, HR1, HX1 channel registers are located in the address range 00_H - 3F_H for
the Host, and in the memory mapped area 3000_H - 303F_H for the DSP. The register
banks for the Host and the DSP are physically separate from each other. The read
registers and write registers are physically separate.
The addresses for these registers are such that a 32-bit sample can be accessed from
the DSP via only two 16-bit read/write operations (16-bit data bus). From the Host, the
access is byte by byte (8-bit data bus).
List of Registers
RC1:
XC1:
HRR1:
HRW1:
HXR1:
HXW1:
32-bit register for audio receive channel 1 (read)
32-bit register for audio transmit channel 1 (write)
32-bit register for reading data from Data Receiver input shift register
32-bit register for writing data to be loaded into Data Receiver input
32-bit register for reading data from Data Transmitter output
32-bit register for writing data to Data Transmitter output shift register
Semiconductor Group
36
Data Sheet 1998-07-01