PEB24902 Datasheet, PDF (33/50 Pages) Siemens Semiconductor Group – Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE

PEB 24902
PEF 24902
Technical Description
Table 8
Specified Data of the Level Detection Circuit
Parameter
Threshold of level detect (4B3T)
DC level of level detect (common mode level)
Limit Values Unit
min. typ. max.
10
30 mV
0
3
V
3.2.7 Power down
Transmit path, receive path and auxiliary functions of the analog line port are switched
to a low power consuming mode when the power down function is activated. This implies
the following:
– The ADC, the relevant pin PDMx is tied to GND.
– The DAC and the output buffer; the pins AOUTx BOUTx are tied to GND.
– The internal DC voltage reference is switched off. The VREFx pin stays at
approximately 2.5 V
– The range and the loop functions are deactivated.
The digital interface, the PLL, and the level detection are not affected by the powerdown.
3.2.8 Power-on-Reset
When applying power to the Quad IEC AFE an internal power-on-reset is generated to
reset the PLL/oscillator and to set CL15 to an input. CL15 remains an input until a clock
signal is detected in the oscillator. As long as no 15.36 MHz master clock is detected the
PLL control functions are switched off.
3.2.9 Reset
The reset is activated by setting pin RES to low. The following functions are reset:
– The reset activates the powerdown of all line ports.
– The synchronization of the digital interface is initialized.
– The data on SDX is ignored during reset.
– SDR is set to low
– The range and the loop functions of all line ports are deactivated
– The PLL is reset to it’s nominal frequency and starts to resynchronize after 130 ns.
All settings are maintained until RES is high and the digital interface is synchronized.
3.3 Digital Interface
On the digital interface transmit and receive data is exchanged as well as control
information for the start-up procedure. The ADC output is transferred to the Quad IEC
Semiconductor Group
33
05.96