C511 Datasheet, PDF (29/43 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

C511 / C513
Power Saving Modes
Two power down modes are available, the idle mode and the power down mode. In the idle mode
only the CPU will be deactivated while in the power down mode the on-chip oscillator is stopped.
The bits PDE and IDLE select the power down mode or the idle mode, respectively. If the power
down mode and the idle mode are set at the same time, power down takes precedence. Table 15
gives a general overview of the power saving modes.
Table 15
Entering and leaving the power saving modes
Mode
Idle mode
Entering
Example
ORL PCON, #01H
Leaving by
– enabled interrupt
– Hardware Reset
Power Down ORL PCON, #02H Hardware Reset
Mode
Remarks
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Oscillators are stopped. Contents
of on-chip RAM and SFR’s are
maintained
(leaving power down mode means
redefinition of SFR’s contents)
In the power down mode of operation, V_CC can be reduced to minimize power consumption. It must
be ensured, however, that V_CC is not reduced before the power down mode is invoked, and that V_CC
is restored to its normal operating level, before the power down mode is terminated. The reset signal
that terminates the power down mode also restarts the oscillator. The reset should not be activated
before V_CC is restored to its normal operating level and must be held active long enough to allow the
oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
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