PEB2045 Datasheet, PDF (27/53 Pages) Siemens Semiconductor Group – Memory Time Switch CMOS (MTSC)

PEB 2045
PEF 2045
Time-slot 31 of the synchronous 2048-kbit/s interface logical line 2 shall be switched to the system
interface logical line 1 of a 2048-kbit/s system, time-slot 2. The system interface logical output
line 1 and the synchronous interface logical input line 2 correspond to the pins OUT 2 and IN 10,
respectively (table 11). The programmed instruction sequence on the data bus for that connection
reads (see table 17 and 18):
00100001
11111010
00010010
In the same application the instruction sequence
00010001
11111101
00010001
connects the time-slot 31 of the system interface logical line 3 (IN 13) to the synchronous interface
logical line 0 (OUT 1) time-slot 2.
Assuming CSR:00_H the frame for input and output lines starts with the rising edge of the SP pulse.
The CSR entry 11011101 shifts the beginning of the frame for the system interface: The input frame
is advanced by 6 data bits because of the shift, but delayed by the 1/2-bit delay facility, resulting in
a 5 1/2-bit period advancement. The output frame structure is delayed by 2 data bit periods and one
half of a device clock period. Figure 15 illustrates these 2 connections for a 4096-kHz device clock.
Figure 15
Example Connections in the Primary Access Configuration
Semiconductor Group
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