PSB2186 Datasheet, PDF (229/240 Pages) Siemens Semiconductor Group – ISDN Subscriber Access Controller for Terminals

Low Level Controller
/* Variables
*/
/* =========
*/
/* Function Declaration
*/
/* ====================
*/
/***************************************************************************/
/*
*/
/* Function: EnaClk_SBC ()
*/
/* Parms : pointer to PEITAB table element
*/
/* purpose : enable clocks for TE configurations
*/
/*
*/
/***************************************************************************/
EXPORT int
EnaClk_SBC (pt)
register PEITAB *pt;
{
unsigned int count, i = 0;
BYTE
BitSet, spcr;
/* Test to see if clocks are
*/
/* actually there. Because the SBC */
/* after reset does not deactivate */
/* its clocks immediately we will */
/* make pretty sure that the clocks */
/* are there before we leave this */
/* routine
*/
BitSet = inp (pt->pt_r_star) & STAR_BVS;
count = 0;
/* we test to see if 6 changes in */
/* the STAR:BVS bit indicating the */
/* reception of at least 3 frames */
/* (6 B channels). If at any time */
/* we fail to find a bit change
*/
/* and the counter i reaches its */
/* maximum then we assume that
*/
/* clocks are no longer present
*/
for (i = 0; i < 500; i++)
if ((inp(pt->pt_r_star) & STAR_BVS) != BitSet)
{
/* Of course we have to reset our */
/* counter every time a bit change */
if (++count > 6)
/* is observed to give the next
*/
return (FALSE);
/* bit change the same amount of */
/* time in which to occur !!!
*/
i = 0;
BitSet = inp (pt->pt_r_star) & STAR_BVS;
}
/* the Bx versions reqire one edge */
/* at FSC.
*/
/* Otherwise the setting of the SPU */
/* has no effect (result: no clock) */
/* The IOM direction control bit */
/* IDC in the ADF1 (SQXR) register */
/* is set before and reset after */
/* the system is clocking
*/
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