C167CR-16F_1 Datasheet, PDF (22/63 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller with 128 KByte Flash EPROM

06May97@14:10h Intermediate Version
C167CR-16F
In Flash Programming Mode (FEE=’0’, FWE=’1’) the C167CR-16F is prepared to program Flash
locations in the way specified by the Word or Double Word Write (WDWW) bit in the FCR. The width
of the programming pulses generated internally is defined by the Internal Flash Timer Clock Control
(CKCTL) bit field of the FCR. The maximum number of programming pulses (PN_max) applied to the
Flash memory is determined by software in the Flash programming algorithm. The chosen values
for CKCTL and PN_max must guarantee a maximum cumulated programming time of 2.5 ms per cell
and a maximum programming pulse width of 128 µs.
If 16-bit programming was selected, the operation will start automatically when a write instruction is
executed, where the first operand specifies the address and the second operand the value to be
programmed:
MOV
[Rw_n], Rw_m
;Program one word
If 32-bit programming was selected, the operation will start automatically when the second of two
subsequent write instructions is executed, which define the doubleword to be programmed.
Note that the destination pointers of both instructions refer to the same even double word address.
The two instructions must be executed without any interruption.
MOV
[Rw_n], Rw_x
MOV
[Rw_n], Rw_y
;Prepare programming of first word
;Start programming of both words
Upon the execution of the second instruction (or the one and only in 16-bit programming mode), the
Flash Busy (FBUSY) bit is automatically set to ‘1’. End of programming can be detected by polling
the FBUSY bit. V_PP must stay within the valid margins during the entire programming process.
At the end of programming the Program-Verify-Mode (PVM) is entered automatically. This mode
allows to check the effect of the erase operation (see description below).
The Flash Verify-Modes Erase-Verify-Mode (EVM) and Program-Verify-Mode (PVM) allow to
verify the effect of an erase or programming operation. In these modes an internally generated
margin voltage is applied to a Flash cell, which makes reading more critical than for standard read
accesses. This ensures safe standard accesses after correct verification.
To get the contents of a Flash word in this mode, it has to be read in a particular way:
MOV
Rw_m, [Rw_n]
...
MOV
Rw_m, [Rw_n]
;First (invalid) read of dedicated cell
;4 µs delay to stabilize...
;...the internal margin voltage
;Second (valid) read of dedicated cell
Such a Flash verify read operation is different from the reading in the standard or in the non-verify
mode. Correct verify reading needs a read operation performed twice on the same cell with an
absolute time delay of 4 µs which is needed to stabilize the internal margin voltage applied to the
cell. To verify that a Flash cell was erased or programmed properly, the value of the second verify
read operation has to be compared against FFFF_H or the target value, respectively.
Clearing bit FWE to ‘0’ exits the Flash verify modes and returns to the Flash non-verify mode.
In Flash non-verify mode all Flash locations can be read as usual (via indirect addressing modes),
which is not possible in Flash programming or Flash erase mode (see EVM and PVM).
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