SDA9251-2X Datasheet, PDF (2/23 Pages) Siemens Semiconductor Group – 868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM)

SDA 9251-2X
Functional Description
The SDA 9251 is a triple port 868 352 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 4 bit to allow for the
storage of 4-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 4-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 1-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 4-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 4-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 4-bit output shift registers A or B is controlled by the serial column address (SAC) which
contains the desired column address and an instruction code (mode bits) for transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 64 memory arrays which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
64 (= 16 x 4) arrays can be randomly addressed, reading or writing 16 x 4 bits at a time. To obtain
the extremely high data rate at the 4-bit wide data input (SDC) and outputs (SQA, SQB), a parallel
to serial conversion is done using shift registers of 16-bit length and 4-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 x 4-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Semiconductor Group
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