HYM72V8020GS-50- Datasheet, PDF (2/12 Pages) Siemens Semiconductor Group – 8M x 72-Bit Dynamic RAM Module

HYM72V8020/30GS-50/-60
8M x 72-ECC Module
The HYM 72V8020/30GS-50/-60 is a 64 MByte DRAM module organized as 8 388 608 words by 72-
bit in a 168-pin, dual read-out, single-in-line package comprising nine HYB3165800AJ/AT 8M × 8
DRAMs in 400 mil wide SOJ or TSOPII - packages mounted together with ceramic decoupling
capacitors on a PC board. All inputs except RAS and DQ are buffered by using BiCMOS buffers/
line drivers.
Each HYB3165800AJ/AT is described in the data sheet and is fully electrically tested and
processed according to Siemens standard quality procedure prior to module assembly. After
assembly onto the board, a further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
Ordering Information
Type
Ordering Code
HYM 72V8020GS-50
HYM 72V8020GS-60
HYM 72V8030GS-50
HYM 72V8030GS-60
Package
L-DIM-168-3
L-DIM-168-3
L-DIM-168-3
L-DIM-168-3
Descriptions
DRAM module (access time 50 ns)
DRAM module (access time 60 ns)
DRAM module (access time 50 ns)
DRAM module (access time 60 ns)
Pin Names
A0-A12,B0
A0-A11,B0
DQ0 - DQ71
RAS0, RAS2
CAS0 , CAS2
WE0, WE2
OE0, OE2
Vcc
Vss
PD1 - PD8
PDE
ID0 , ID1
N.C.
Row Address Inputs
Column Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Output Enable
Power (+3.3 Volt)
Ground
Presence Detect Pins
Presence Detect Enable
ID indentification bit
No Connection
Presence-Detect and ID-pin Truth Table:
Module
ID0 ID1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
HYM 728020/30GS-50 Vss Vss 1
0
1
1
0
0
0
0
HYM 728020/30GS-60 Vss Vss 1
0
1
1
0
1
1
0
Note: 1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high
level all PD terminal are in tri-state.
Semiconductor Group
2